Led display device and method for operating the same

ABSTRACT

An LED display device includes a transmitter having a memory and a pixel mapping table, a plurality of first receivers coupled to the transmitter, a plurality of second receiver modules, and a plurality of LED driver groups. A unique address is assigned to a data packet with a use of the pixel mapping table. The data packet has a set of field information and the set of field information includes the unique address. Each of the second receiver modules is coupled to at least one of the first receivers and includes a plurality of second receivers. None of the plurality of second receivers comprises a pixel mapping memory. Each of the LED driver groups is coupled to one of the plurality of second receivers and includes a plurality of LED drivers.

FIELD OF THE DISCLOSURE

This disclosure relates generally to an LED display device and a method for operating the same. In particular, this disclosure relates to an LED display device using a transmitter having a memory and a pixel mapping table.

BACKGROUND OF THE DISCLOSURE

Light emitting diode (LED) is widely used for displaying information and messages. LED is a solid-state device that converts electric energy to light. LED display panels provide a higher level of brightness and greater optical efficiency as compared to other types of display panels. Recently, LED display panels have been used to make large indoor or outdoor display panels and televisions.

The design, fabrication, and operation of a large LED display panel face numerous technical challenges. For example, the size of an LED display panel can be as large as around 7.35 m×4.1 m. With such large display panels, it becomes difficult to send a set of data to designated LED drivers across the LED display panels in a synchronous manner. The set of data can include configuration control bits and pulse-code modulation (PCM) data. Such data control the brightness, color depth, and on-and-off of the LED display.

FIG. 1A is a schematic block diagram of an LED system 1 having a plurality of receiver cards 13, each of the receiver cards 13 being connected to a plurality of LED drivers 14. Referring to FIG. 1, the LED system 1 includes a video source 10, a SendBox 12, a plurality of receiver cards 13, and a plurality of LED drivers 14. To transmit a set of data to a designated set of LED drivers 14, the LED system 1 requires the SendBox 12 and the plurality of receiver cards 13. Depending on the configuration of the LED system, the total number of receiver cards 13 may vary. A receiver card 13 receives data from the SendBox 12 via a gigabit Ethernet port 11. A set of LED drivers 14 have access to a serially arranged set of plurality of receiver cards 13 to read the data. Each set of LED drivers 14 corresponds to a receiver card 13. Thus, as the number of LED drivers 14 grows, the number of gigabit Ethernet ports 11 designated to the plurality of receiver cards 13 increases.

FIG. 1B is a schematic block diagram of a receiver card 13 a connected to another receiver card 13 b and the two receiver cards connected to a set of LED drivers 14 a and 14 b, respectively. The diagram is an enlargement of two receiver cards 13 and the connected set of LED drivers 14 shown in FIG. 1A. It is a close-up depiction of two linked receiver cards. All other receiver cards in a serially arranged plurality of receiver cards are configured in the manner showing in FIG. 1B. The two receiver cards are connected via a GigaPHY (hereafter “GPHY”) link which requires gigabit Ethernet ports and transformers on both the sending and the receiving end of the receiver cards. As the number of receiver cards grows, the number of GPHY links between the receiver cards increases. Furthermore, each of the receiver cards requires a memory for pixel mapping. Referring to FIG. 1B, a receiver card 13 a is realized by a field-programmable gate array (FPGA) device with on-board frame buffer for pixel mapping and buffer usage. GPHY 11 and transformer 11 a are configured for a link. A large-scale array of LED driver chip using GPHY technology requires a heavy volume of pins.

FIG. 2 is a schematic block diagram of an LED system 1′. Referring to FIG. 2, LED system 1′ includes a video processor 10, a transmitter 11, a receiver card 13, and a plurality of LED drivers 14. The receiver card 13 receives data from the transmitter 11 via a GPHY link. After receiving data designated thereto, the receiver card 13 distributes the received data to the plurality of LED drivers 14 attached thereto. Such data distribution necessitates pixel mapping to ensure that the initially transmitted data is received and reconstructed in desired order to display the final image from the video source on the LED display panel.

The memory required for the pixel mapping function is often located in the receiver card 13 as shown in FIG. 2. This creates at least three following problems. First, the receiver card 13 needs additional space for the placement of memory required for pixel mapping. The size of the additional memory physically limit the size of an ultrathin LED display panel. Second, the additional memory placed in the receiver card 13 for implementation of the pixel mapping function significantly increases production costs of LED display panels. Third, the existence of an additional memory in the receiver card 13 creates an additional frame latency during pixel mapping, causing potential delays when displaying images on the LED display panel. Accordingly, a display device, a method for transmitting data packet, and a light-emitting diode (LED) system that overcome the above described shortcomings are needed.

SUMMARY OF THE DISCLOSURE

In view of the aforementioned problems, the present disclosure provides an LED display device and a method for operating the LED display device. An LED display device is provided according to an embodiment of the present disclosure. An LED display device includes a transmitter having a memory and a pixel mapping table, wherein a unique address is assigned to a data packet with a use of the pixel mapping table and wherein the data packet has a set of field information and the set of field information includes the unique address, a plurality of first receivers coupled to the transmitter, a plurality of second receiver modules, wherein each of the second receiver modules is coupled to at least one of the first receivers and comprises a plurality of second receivers, and wherein none of the plurality of second receivers comprises a pixel mapping memory, and a plurality of LED driver groups, wherein each of the LED driver groups is coupled to one of the plurality of second receivers and comprises a plurality of LED drivers.

The memory is a double data rate synchronous dynamic random-access memory (DDR SRAM).

The transmitter may transmit the data packet and each of the second receivers may read the set of field information transmitted from the transmitter and determine whether the set of field information is designated thereto. The set of field information is configured to be changed sequentially by adding or subtracting a predetermined value therefrom when enters in or exit out of each of the second receivers.

The second receivers may be serially arranged in one of the plurality of first receiver modules. The set of field information includes a first field information and a second field information. The first field information has a first number subtracted one from a total number of the serially arranged second receivers, and the second field information has a second number of a sequential order number of a designated second receiver.

Each one of the second receivers may compare the first field information with the second field information and determine whether the set of field information is designated thereto if the first field information and the second field information.

The second receivers may be serially arranged in one of the plurality of first receiver modules. The set of field information includes a first field information and a second field information. The first field information includes a first value and the second field information includes a second value. Each of the second receivers is configured to compare the first value to the second field value, and when the first number is not the same with the second number, the first number is increased by an increment of a value one (1) and the set of field information is transmitted to adjacent second receiver, and the second field information has a second number of a sequential order number of a designated second receiver.

The at least one of the first receivers communicates with at least one of the second receivers via a Low Voltage Differential Signaling (LVDS) connection. At least one of the first receivers communicates with at least one of the second receivers via a LVDS connection.

The data packet includes a first segment including the set of field information, a second segment including data information, and a third segment including the set of field information. The first, second, and third segments are sequentially arranged. The first segment includes a start of frame and a data mode information. The third segment further comprises an end of frame and the data mode information.

According to another embodiment of the present disclosure, a method for operating an LED display device is provided. The method includes transmitting a data packet from a transmitter to a plurality of first receivers, wherein the transmitter has a memory and a pixel mapping table, and a unique address is assigned to a data packet with a use of the pixel mapping table, and wherein the data packet has a set of field information and the set of field information includes the unique address, transmitting the data packet from the plurality of first receivers to a plurality of second receiver modules, wherein each of the second receiver modules is coupled to at least one of the first receivers and comprises a plurality of second receivers, and wherein none of the plurality of second receivers comprises a pixel mapping memory, and transmitting the data packet the plurality of second receiver modules to a plurality of LED driver groups, wherein each of the LED driver groups is coupled to one of the plurality of second receivers and comprises a plurality of LED drivers.

The memory is a double data rate synchronous dynamic random-access memory (DDR SRAM).

The transmitter may transmit the data packet and each of the second receivers may read the set of field information transmitted from the transmitter and determine whether the set of field information is designated thereto. The set of field information is configured to be changed sequentially by adding or subtracting a predetermined value therefrom when enters in or exit out of each of the second receivers.

The second receivers may be serially arranged in one of the plurality of first receiver modules. The set of field information includes a first field information and a second field information. The first field information has a first number subtracted one from a total number of the serially arranged second receivers, and the second field information has a second number of a sequential order number of a designated second receiver.

Each one of the second receivers may compare the first field information with the second field information and determine whether the set of field information is designated thereto if the first field information and the second field information.

The second receivers may be serially arranged in one of the plurality of first receiver modules. The set of field information includes a first field information and a second field information. The first field information includes a first value and the second field information includes a second value. Each of the second receivers is configured to compare the first value to the second field value, and when the first number is not the same with the second number, the first number is increased by an increment of a value one (1) and the set of field information is transmitted to adjacent second receiver, and the second field information has a second number of a sequential order number of a designated second receiver.

The at least one of the first receivers communicates with at least one of the second receivers via a Low Voltage Differential Signaling (LVDS) connection. At least one of the first receivers communicates with at least one of the second receivers via a LVDS connection.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic block diagram of an LED system having a plurality of receiver cards, each of the receiver cards being connected to a plurality of LED drivers.

FIG. 1B is a schematic block diagram showing a receiver card connected to another receiver card. Each receiver card is connected to a set of LED drivers.

FIG. 2 is a schematic block diagram of an LED system.

FIG. 3 is a schematic block diagram showing a configuration of an LED system.

FIG. 4 is a schematic block diagram showing a hierarchical configuration of the LED system according to the embodiment of the present disclosure.

FIG. 5 is a schematic block diagram showing first and second receivers shown in FIG. 4 arranged in the LED display panel according to the embodiment of the present disclosure.

FIG. 6 is a detailed schematic block diagram illustrating one set of the first and second receivers, and their connections to a plurality of LED drivers according to the embodiment of the present disclosure.

FIG. 7 is a schematic block diagram of adjacent first receivers connected serially via a transformerless wire link and plurality of LED drivers connected to each of the first receivers.

FIG. 8 is a schematic block diagram of two second receivers connected serially via a transformerless wire link and a plurality of LED drivers connected to each of the first receivers.

FIG. 9 is a schematic block diagram showing a configuration of an LED system.

FIG. 10 is a block diagram illustrating a structure of a configuration data packet.

FIG. 11 is a block diagram illustrating a structure of a configuration data packet.

FIG. 12 is a block diagram illustrating a structure of an image data packet.

FIGS. 13A and 13B are block diagrams illustrating a method to change a first field information and a second field information.

FIG. 14 is a block diagram showing a calculation of V_(sync) signal delay value.

FIG. 15 is a graph showing a configuration data modulation and synchronization thereof.

FIG. 16 is a schematic flowchart of the method for transmitting data packet using an LED display device that includes transmitter, at least one first receiver, and a plurality of second receiver modules.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout the several views. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. Terms used herein are for descriptive purposes only and are not intended to limit the scope of the disclosure. The terms “comprises” and/or “comprising” are used to specify the presence of stated elements, steps, operations, and/or components, but do not preclude the presence or addition of one or more other elements, steps, operations, and/or components. The terms “first,” “second,” and the like may be used to describe various elements, but do not limit the elements. Such terms are only used to distinguish one element from another. These and/or other aspects become apparent and are more readily appreciated by those of ordinary skill in the art from the following description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.

An embodiment of the present disclosure is described with reference to FIGS. 3-8. FIG. 3 is a schematic block diagram showing a configuration of an LED system 100. FIG. 4 is a schematic block diagram showing a hierarchical configuration of the LED system 100 according to the embodiment of the present disclosure. FIG. 5 is a schematic block diagram showing first and second receivers shown in FIG. 4 arranged in the LED display panel according to the embodiment of the present disclosure. FIG. 6 is a detailed schematic block diagram illustrating one set of the first receivers 120 a and second receivers and 130 a 6, and their connections to a plurality of LED drivers 140 a, 140 b, 140 c, 140 d, and 140 e according to the embodiment of the present disclosure. FIG. 7 is a schematic block diagram of adjacent second receivers 130 a 1 and 130 a 2 connected serially via a transformerless wire link 150 and plurality of LED drivers 140 connected to each of the second receivers 130 a 1 and 130 a 2. FIG. 8 is a schematic block diagram of two second receivers 130 a 1 and 130 a 2 connected serially via a transformerless wire link 150 and a plurality of LED drivers 140 a connected to each of the second receivers 130.

LED system 100 includes a transmitter 110, a plurality of first receivers 120, a plurality of second receivers 130, a plurality of LED drivers 140, and a plurality of transformerless wire link 150. According to the embodiment of the present disclosure, LED system 100 has a compact structure because the plurality of transformerless wire link 150 enable the connections of the plurality of first receivers 120 and the plurality of second receivers 130 without transformers.

For the purpose of simplicity, unless otherwise indicated herein, reference numeral 120 refers to a plural number of first receivers while a specific first receiver is designated as the reference numeral 120 followed by an alphabet, e.g., 120 a. Likewise, reference numeral 130 refers to a plural number of second receivers. A second receiver module containing a plural number of second receivers is referred to as the reference numeral 130 followed by an alphabet, e.g., 130 a. A specific second receiver is referred to as the reference numeral 130 followed by an alphabet plus a number, e.g., 130 a 1. Likewise, reference numeral 140 refers to a plural number of LED drivers while a specific LED driver is referred to as the reference numeral 140 followed by an alphabet plus a number, e.g., 140 a 1. AN LED driver group containing a plural number of LED drivers is referred to as 140 a.

In prior art as illustrated in FIG. 1B, a SendBox 12 (not shown in figure) transmits data to receiver cards 13 a and 13 b via GPHY link 11. GPHY generally requires electrical insulation between port device circuits, e.g., using transformers 11 a

According to the present disclosure, the GPHY link 11 is replaced with the transformerless wire link 150. As seen in FIG. 3, for instance, one of the plurality of first receivers 120 is connected to the plurality of second receivers 130 via the transformerless wire link 150. Adjacent second receivers 130 a and 130 b are connected to one another via the transformerless wire link 150 as well.

Now, referring to FIGS. 3, 7 and 8, the transmitter 110 receives data from a video processor 10, such as a VCR player, a camcorder, a HD-DVD player, and/or a satellite. The transmitter 110 receives data from a video processor 10 via a data port. The data port can be, for example, HDMI (High-Definition Multimedia Interface). HDMI has been selected for illustrative purpose only, and the transmitter 110 can receive data via other types of data ports.

The plurality of first receivers 120 receive data from the transmitter 110 and then distribute data to their respective locations in the plurality of second receivers 130, i.e. 130 a and 130 b, which are connected serially or parallelly. After receiving data, each of the plurality of second receivers 130 further distributes the received data to the sets of LED drivers 140, i.e. 140 a and 140 b attached thereto. The transformerless wire link 150 is configured to connect the plurality of first receivers 120 and the plurality of second receivers 130 without transformers 11 a.

The transformerless wire link 150 is a functional block or wire which can be used in high speed communication without transformers. The transformerless wire link 150 can convert data between serial data and parallel interfaces in either direction. The transformerless wire link 150 can be used for short-distance link and can include, for instance, a serializer/deserializer (SerDes) link. The transmitter 110 is usually located at a distance from the first receivers 120, e.g., up to 100 m. The connection between the transmitter 110 and the first receivers 120 is often established by a GPHY link. The first receivers 120 and the second receivers 130 are located within a short-distance, e.g., less than 50 m, less than 20 m, less than 10 m, less than 5 m, and are connected via the transformerless wire link 150.

Additionally, the transformerless wire link 150 is less expensive than GPHY because it does not require transformers. The transformerless wire link 150 such as SerDes can readily be integrated into ASIC chip and thus enable the use of smaller receiver ASIC chips. With the introduction of the transformerless wire link 150, the LED display panel can be made as a total ASIC solution. Furthermore, the adoption of the transformerless wire link 150 reduces the size of the plurality of first receivers 120 and the plurality of second receivers 130 and in turn reduces the size of the LED system 100.

SerDes is only one example of the transformerless wire link 150. Other short-distance link technologies may be employed for implementing the transformerless wire link 150. Referring now to FIG. 4, one of the plurality of first receivers 120 a is linked to one of the plurality of second receivers 130 a 1 via the transformerless wire link 150. The second receiver 130 a 1 is linked to its adjacent receiver 130 a 2 via the transformerless wire link 150. The first receivers 120 and second receivers 130 can be arranged serially or in parallel and can be linked using the transformerless wire link 150.

Referring to FIGS. 3, 7, and 8, one of examples of the LED system 100 using transformerless wire link 150 is depicted. As an example, the LED system 100 receives video data has a bandwidth of 7.46 Gbps (1920×1080×30×120); the LED driver 140 has clock rate of 6.4 MHz; and the SerDes has clock rate up to 307.2 MHz. SerDes is used herein only as a non-limiting example of the transformerless wire link 150.

The video data having a bandwidth of 7.46 Gbps (1920×1080×30×120) has 30 bit per pixel color and is received from the video processor 10. If the 30 bit per pixel color is processed in a double word (32-bit) format, it is more efficient and easy to handle at the LED system 100. If 32-bit format is used, 1/16 bandwidth (2 bit) may be lost. In such a case, for calculation purpose, a practical bandwidth over this video data is 7.96 Gbps (1920×1080×32×120), which is close to 8 Gbps. However, because Ethernet packets require extra headers and inter packet gaps, the total video data to be processed would exceed 8 Gbps. Such bandwidth requires at least nine (9) GPHY lanes. When nine (9) GPHY lanes are used, each GPHY lane carries 884.7 Mbps (7.96 Gbps/9), which is transmitted to the plurality of first receivers 120. The data of 884.7 Mbps carried by each GPHY lane can be converted for SerDes using 8 B/10 B encoder for DC-balanced code. Examplary links used for SerDes technology include PCI-e, SATA, USB3.0, RAPID I/O, CEI-6G-SR, DP, VbyOne, XAUI, SGMII etc. After the 8 B/10 B encoder, the 884.7 Mbps is converted into 1.106 Gbps. To process 1.106 Gbps, 1.25 Gbps SerDes such as SGMII can be adopted to carry all information.

In another example, a data rate of 307.2 Mbps can be used instead of 1.25 Gbps SerDes. With the 307.2 Mbps data rate, four (4) SerDes Ports per each of the plurality of first receivers 120 are required to process the 1.106 Gbps. At the plurality of second receivers 130, the data rate of 307.2 Mbps is converted into 30.72 MByte/sec through 10 B/8 B decoder. Counting by D-word, 7.68 MHz (30.72 M/4) is obtained. Here, a D-word is 32-bit which can carry 30-bit (10-bit RGB) with 2 bit redundant. Thus, 7.68 MHz becomes a transfer pixel rate. As the clock rate of LED driver 140 is 6.4 MHz, the 7.68 MHz pixel rate obtained through SerDes provides enough speed to cover the required clock rate of 6.4 MHz at LED driver 140. Such a clock rate allows DC coupling and simplifies the PCB board. Each of the first receivers 120 and each of the second receivers 130 can employ 8 B/10 B encode in transmit side and 10 B/8 B decode in receiver side. So that for the retimed portion, each of the second receivers 130 can do 8 B/10 B encode so as to transmit the data to adjacent second receiver 130.

8 B/10 B code is a code book to map byte data into 10-bit code book. The code book defines a plurality of control codes of K-code. For example, D-code may refer to data codes while K-code may refer to control codes. Transformerless wire link 150 such as SerDes can employ protocols using K-code as frame wrapper to package a frame before a transmission. Regarding K-codes, for example, K28.5 is about IDLE (primitive); K27.7 is about Start of Frame primitive; K29.7 is about End of Frame primitive; and K28.3 is about V_(sync) primitive.

As can be seen in FIG. 7, the transformerless wire link 150 employs DC-coupled low voltage differential signal (LVDS) technology and low-bandwidth phase-locked loop (PLL). The source clock is provided by the plurality of first receivers 120 and passed along the transformerless wire link 150. The transformerless wire link 150 connects to a PLL 131 disposed in the second receiver 130 a 1.

The PLL 131 is a control system that generates an output signal whose phase is related to the phase of an input signal. For example, while there are several possible configurations, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is fed back toward the input forming a loop.

The PLL 131 provides all required clocks for the internal LVDS receiver/transmitter circuits in second receiver 130 a 1 as well as for adjacent second receiver 130 a 1 and all subsequent second receivers linked serially in the receiver chip chain. The PLL 131 of the second receiver 130 a 1 also generates a low jitter clock for the next receiver chip 130 a 2. This architecture requires no additional components (such as transformer 11 a), between any two adjacent first receivers 130 a 1 and 130 a 2 along a serially arranged receiver chip chain except the transformerless wire link 150. Thus, this architecture according to the present disclosure eliminates numerous GPHY ports and transformers. By eliminating GPHY ports and transformers, the plurality of first receivers 120 and the plurality of second receivers 130 can be downsized. Productions costs are also reduced and the achievement of an ultra-thin LED display panel becomes possible.

As shown in FIG. 3, first receivers 120 is coupled to transmitter 110. The video processor 10 is connected to the transmitter 110 via HDMI. HDMI has been selected for an illustrative purpose only; other link types may be used to connect the video source 10 with the transmitter 110. Transmitter 110 sends various signals and data from the contents sources to first receivers 120. First receivers 120 can have plural input and output ports (not shown), which are connected to the transmitter 110. Each of input and output ports can have CAT5/CAT6 cable with gigabits data rate when first receivers 120 communicate with transmitter 110. First receivers 120 can include L number of first receivers. For the purpose of exemplary illustration only and as shown in FIG. 3, first receiver 120 includes nine (9) first receivers 120 a, 120 b, 120 c, 120 d, 120 e, 120 f, 120 g, 120 h, and 120 i.

As shown in FIG. 4, second receivers 130 are coupled to a corresponding first receiver 120 in a parallel manner. Second receivers 130 receive various signals and data from first receivers 120, and transmit the same to LED drivers 140.

Second receivers 130 may have N number of second receiver modules. As shown in FIG. 5, for instance, second receivers 130 have four (4) second receiver modules 130 a, 130 b, 130 c, and 130 d.

Each of L number of first receivers 120 is coupled to every of N number of second receiver modules in a parallel manner. For instance, first receiver 120 a is coupled to each one of four (4) second receiver modules 130 a, 130 b, 130 c, and 130 d. N number of second receiver modules e.g. 130 a, 130 b, 130 c, and 130 d, may be parallelly coupled to first receiver 120 a.

First receiver 120 a transmits data to its parallelly coupled four (4) second receiver modules 130 a, 130 b, 130 c, and 130 d using a time domain multiplexing division access protocol. First receiver 120 a transmits data to the coupled receiver modules using time domain multiplexing. Then, each second receiver module 130 a, 130 b, 130 c, and 130 d retrieves its own time slot information to process the data designated thereto.

Each of N number of second receiver modules, e.g. 130 a, 130 b, 130 c, and 130 d may include M number of second receivers, e.g. 130 a 1, 130 a 2, 130 a 3, 130 a 4, 130 a 5, and 130 a 6. M number of second receivers may be serially arranged. Thus, with respect to the number of first receivers 120 and second receivers 130, there are L number of first receivers 120 and L×M×N number of second receivers 130. Second receivers 130 can be configured to support FCCL (full content cycle lighting), Calibration data, and Gamma Table correction.

Each of first receivers 120 can transmit data in Low Voltage Differential Signaling (LVDS) format to second receivers 130. LVDS may be transmitted at 307.2 MHz signal rate, and when 8 B/10 B code is used, real data rate may be around 245.76 M. 8 B/10 B encoding addresses the coding process that each incoming octet passes down and encodes it into a ten-bit code group. Each octet is given a code group name according to the bit arrangement.

The configuration shown in FIG. 4 has technical advantages because it requires less transformers and gigabit Ethernet ports. As the prior art example illustrated in FIG. 1A shows, each of the receiver cards 13 requires a transformer and a gigabit Ethernet port. The resulting large number of transformers and gigabit Ethernet ports generate EMI and occupy valuable space. However, according to the present disclosure, only first receivers 120 requires transformers and gigabit Ethernet ports to communicate with the transmitter. In other words, only L number of first receivers 120, instead of L×(M×N) receivers, requires transformers and gigabit Ethernet ports. That is because, as was shown in FIG. 3, each of first receivers 120 (referred to as bridge chip in FIG. 3) can transmit data in Low Voltage Differential Signaling (LVDS) format to second receivers 130 (referred to as receiver chip in FIG. 3), instead of Gigabit Ethernet ports. Accordingly, having two types of receiver units and adopting LVDS format for communication between them reduces the number of transformers and gigabit Ethernet ports. Another advantage according to the present disclosure is that the conventional sending card, first receiver cards, and second receiver cards can be replaced by ASIC chips, which occupies a comparatively small space. Thus, LED display panels according to the present disclosure can be configured to have a very compact structure.

LED drivers 140 are electrical devices that regulate the power or signal to LEDs or string(s) of LEDs. Each of second receivers, e.g. 130 a 6 is coupled to each one of 0 number of LED driver groups, e.g. 140 a, 140 b, 140 c, 140 d, and 140 e. Each of 0 number of LED driver groups, e.g. 140 a includes P number of LED drivers, e.g. 140 a 1, 140 a 2, and 140 a 3. In other words, first module's sixth (6^(th)) second receiver 130 a 6 is coupled to fifteen (15) LED drivers (five LED driver groups×three LED drivers). LED driver Groups 140 a, 140 b, 140 c, 140 d, and 140 e are parallelly coupled to second receivers, e.g. 130 a 6. LED drivers 140 a 1, 140 a 2, and 140 a 3 are serially arranged.

FIG. 5 is a schematic block diagram showing an arrangement of first receivers 120 and second receivers 130 across the LED display panel (not shown). An exemplary LED display panel may have a resolution of 1920×1080 pixels. According to one aspect of the disclosure, as shown in FIG. 5, there are nine (9) first receivers 120 a, 120 b, 120 c, 120 d, 120 e, 120 f, 120 g, 120 h, and 120 i. Four second receiver modules 130 a, 130 b, 130 c, and 130 d are coupled to first receiver 120 a. Each of second receiver modules 130 a, 130 b, 130 c, and 130 d includes six (6) second receivers, e.g. 130 a 1, 130 a 2, 130 a 3, 130 a 4, 130 a 5, and 130 a 6. Since first receivers 120 and second receivers 130 may be disposed on the display device as chip components without transformers, the size of the LED system 100 can be minimized, and thus a compact LED display panel can be fabricated.

Transmitter 110 can be any form of sending cards, sending boxes, or personal computers with Ethernet gigabit ports. The plurality of transmitters 110 can be disposed outside of LED display panel. Alternatively, transmitters 110 can be a gigabit port input and LVDS port with Clock Date Recovery (CDR) output, which are implemented in FPGA and/or ASIC. In this case, transmitters 110 can also be disposed on LED display panel.

The LED display panel can include a great number of discrete LED pixels and processors. Inconsistencies among these components may result in variations in, e.g., color and luminance across the display so that a calibration process is needed.

After the calibration process, the calibration data can be stored in a flash memory so that, while in a power up stage as requested by a controller, the calibration data can be used as reference data for each of LED drivers 140 so as to make the LED display panel more uniform in color and luminance.

FIG. 6 is a detailed schematic block diagram showing one set of the first receiver 120 a, sixth (6th) second receiver 130 a 6, and LED drivers 140. The first receiver 120 a can be coupled to 130 a 6 as well as the first (1^(st)), second (2^(nd)), third (3^(rd)), fourth (4^(th)), and fifth (5^(th)) second receiver 130 a 1, 130 a 2, 130 a 3, 130 a 4, and 130 a 5. FIG. 6 shows that first receiver 120 a is coupled to sixth (6^(th)) second receiver 130 a 6. Sixth (6^(th)) second receiver 130 a 6 is coupled to five LED driver groups 140 a, 140 b, 140 c, 140 d, and 140 e. Only sixth (6^(th)) second receiver 130 a 6 is described for illustrative purposes; however, each one of second receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, and 130 a 5 can have same or similar function therewith. Sixth (6^(th)) second receiver 130 a 6 includes processor 130 a 6 p. Processor 130 a 6 p can include a register memory. Processor 130 a 6 p and the register memory can be coupled to first memories 130 a 6 m 1, 130 a 6 m 2, 130 a 6 m 3, 130 a 6 m 4, and 130 a 6 m 5. First memories 130 a 6 m 1, 130 a 6 m 2, 130 a 6 m 3, 130 a 6 m 4, and 130 a 6 m 5 are parallelly arranged among themselves and have static random access memories (SRAMs).

Data distribution requires pixel mapping for the image sent from the initial video processor 10 to appear unaltered on the LED display panel (not shown). Conventionally, pixel mapping is done by both the sendbox 12 and the receiver cards 13. The present disclosure places the pixel mapping function s in the transmitter 110.

FIG. 9 is a schematic block diagram showing a configuration of an LED system 101. It includes a transmitter 110, a plurality of first receivers 120, a plurality of second receivers 130, and a plurality of LED drivers 140. Transmitter 110 includes a memory 111 and a pixel-mapping look up table 113.

FIG. 9 illustrates the interleaved pixel mapping algorithm of the current disclosure. Video processor 10 sends pixels to transmitter 110. During frame buffer time, small amounts of pixel data are saved in an interleaved manner into calculated locations in the memory 111, which is a double data rate synchronous dynamic random-access memory (DDR SRAM) positioned in transmitter 110. The stored interleaved pixel data in the frame buffer is then fetched and sent to first receivers 120. From first receivers 120, the interleaved pixel data is sent to its respective location in each of the second receivers 130 a and/or 130 b, depending upon the intended location for transmission. Upon receiving the interleaved pixel data, the second receiver 130 a or 130 b relays the data to the final destination, LED drivers 140 a or 140 b.

The configuration in FIG. 9 has technical advantages over that of the prior art in the following aspects. In the prior art, each receiver card is responsible for the pixel mapping function. Thus, each receiver card needs a significantly large external memory. In contrast, as shown in FIG. 9, the memory 111 in the transmitter 110 is now exclusively responsible for the pixel mapping function. Consequently, the second receivers 130 does not require a memory equivalent to the memory 111.

The link between the first receivers 120 and the second receivers 130 is a time domain multiplexing division access protocol. Thus, data is broadcasted to media in time domain multiplexing. Each of the second receivers 130 is configured to retrieve its own time slot information to process.

This mechanism can be adopted in shared bus or wireless configuration. The connection can be retimed point to point to maintain high speed of the transformerless wire link 150 including SerDes. Accordingly, a mechanism for self-addressing is a necessity so that each of the second receivers 130 can retrieve its own time slot.

An interleaved pixel mapping refers to a pixel mapping using an interleaved method. In a LCD Display System, a pixel mapping or an interleaved pixel mapping is not required because the video data from video processor 10 is carried in a sequential manner from 1^(st) line to the last line to complete a frame. However, with respect to LED display system 101, video data from video processor 10 is not directly connected to a final LED display panel. Instead, the video data need to be distributed through the transmitter 110 (sendbox), the first receivers 120 (bridge chip), the second receivers 130 (receiver card), and LED driver 140. Thus, in LED display system 101, the video data is broken down into a plurality of data segments from a transmission end. The plurality of data segments are restored at the receiving end to constitute a complete image. This process is called an interleaved pixel mapping. The interleaved pixel mapping can be performed by an automatic address mapping at the first receivers 120. The first receivers 120 can transmit a complete frame buffer so that it can be distributed via data channel.

Referring to FIG. 9, video data is first sent from video processor 100 to transmitter 110 (SendBox). In the interleaved manner described previously, data is broken up into segments and saved to memory 111, which is typically a DDR SDRAM. Before the interleaved pixel data is saved to memory 111, each interleaved pixel data goes through pixel-mapping lookup-table 113, which is a database and stores pixel data in a predefined order. Without the pixel-mapping lookup-table 113, the interleaved pixel data would be stored in a random manner in memory 111, making it impossible for the first receivers 120, the second receivers 130, and set of LED drivers 140 to recognize data forwarded thereto. For instance, when pixel_data_to_port_0 in interleaved pixel data is sent from video processor 10 to transmitter 110, pixel_data_to_port_0 initially goes through pixel-mapping-lookup-table 113 and is given a unique address. Then, pixel_data_to_port_0 with unique address attached is saved to memory 111. Afterwards, pixel_data_to_port_0 with unique address attached is now sent from memory 111 in transmitter 110 (SendBox) to the plurality of the first receivers (bridge chips) 120. Upon receiving of data, each of the first receivers 120 pass data to the designated second receivers 130. Upon receiving of data, the designated second receivers 130 forwards data to the final destination—the designated plurality of LED driver 140. Data reception and forwarding all occur in the manner already described previously in this disclosure.

FIG. 10 is a block diagram illustrating a structure of a configuration data packet 200. A configuration data packet 200 includes a comma 202, a first segment 204, a payload 206, and a second segment 208, and a fourth segment 209. The data packet 200 has a D-word (32-bit) format, which can be 40-bit after 8 B/10 B encoded. The comma 202 serves to fill the gap between valid frames. A plurality of the commas 202 can be inserted between frames. The first segment 204, the payload 206, and the second segment 208 are data type to be delivered. The frame is encapsulated by the first segment 204 (SOF) and the second segment 208(EOF) can be constituted by one D-word. The payload 206 may have a multitude of D-words.

The first segment 204, for instance, includes information regarding the automatic address, which can be used for finding the final designation of the relevant data. The first segment 204 can be composed of 4 bytes (D-word).

First segment 204 includes a start of frame 204 a, set of field information 204 b, target receiver chip information 204 c, and data mode information 204 d. Start of frame 204 a is K-code (K27.7). Set of field information 204 b is defined as chain ID. Chain ID is 0 from the first receivers 120. While doing the retime process and delivered to adjacent second receivers 130, the retime logic add value one (1) (or minus value one). Target receiver chip information 204 c has a target receiver chip ID. Data mode information 204 d includes information of the data-type, which defines payload sub-target device and format. The first segment 204 includes the information about the final destination from the first receivers 120 to LED driver 140. The fourth segment 209 includes a V_(sync) signal data. Each and every one of second receivers 130 can use a V_(sync) action with the fourth segment 209.

Referring to FIGS. 11 and 12, another example of data packets 210 and 220 is described. FIG. 11 is a block diagram illustrating a structure of a configuration data packet 210. FIG. 12 is a block diagram illustrating a structure of an image data packet 220. PWM data, configuration register data, and flash memory data can be transmitted from each of first receivers 120 to plurality of second receivers 130. It is important to transmit such data to the designated second receiver or LED driver in a synchronous manner. FIGS. 11 and 12 illustrate a data packet structure that transmits data from first receivers 120 to designated second receivers 130 in a synchronous manner. In a similar manner, data can be transmitted from second receivers 130 to LED drivers 140.

Each of configuration data packet 210 and image data packet 220 includes a comma 212 and 222, a first segment 214 and 224, a second segment 216 and 226, and a third segment 218 and 228. Configuration data packet 210 and image data packet 220 contain configuration data and image data, respectively. Image data include PWM and flash memory, LED Driver's configuration and control data. Since configuration data packet 210 and image data packet 220 have similar a data structure, for the purpose of simplicity, configuration data packet 210 and image date packet 220 are described together below.

A comma 212 and 222 is a special sequence of bits, and works as a preamble of the data packet. The notation used for ordered sets is similar to that used for code groups. Code groups are written as either /Dx.y/ or /Kx.y/ as shown in FIGS. 8 and 9. Although FIG. 11 and FIG. 12 depict 4× comma for illustrative purposes. Embodiments according to the present description may have, for instance, 5×, 6×, 7×, 8×, and 10× comma.

In particular, ordered sets of K28.5 is used in comma 212 and 222 as the first code group. K28.5 is a pre-defined unique data pattern. The reception of K28.5 will not happen during data packet process unless there is a data error. Thus, K28.5 can be used with specific ordered sets such as a starting point of an idle or configuration.

First segment 214 and 224 includes a start of frame 214 a and 224 a, set of field information 214 b, 214 c, 224 b, and 224 c, and data mode information 214 d and 224 d. A data packet on the wire is called a frame, which consists of binary data. A start of frame 214 a and 224 a marks a starting point of packet frames. The set of field information 214 b, 214 c, 224 b, and 224 c is described in detail with reference to FIGS. 10A and 10B. Data mode information 214 d and 224 d indicates whether the data information is configuration data or image data.

Second segment 216 and 226 contains data information. For example, second segment of configuration data packet 216 includes configuration information. Configuration information includes index and operation information, and configuration data. For example, operation information includes read/write instructions. Index information includes whether the designation of the data packet is second receivers 130 or LED driver 140. Configuration data includes detailed configuration data 210 and a part of configuration data space can be reserved for future use. Second segment of image data packet 226 includes image data such as red-green-blue (RGB) data.

Third segment 218 and 228 includes an end of frame 218 a and 228 a, a set of field information 218 b, 218 c, 228 b, and 228 c, and data mode information 218 d and 228 d. Third segment 218 and 228 has similar structure with first segment 214 and 224. End of frame 218 a and 228 a marks an ending point of packet frames.

Referring now to FIG. 11 and FIG. 13A, the set of field information 214 b, 214 c, 218 b, and 218 c is described. Configuration data packet in first segment 214 b and 214 c has same structure and value with configuration data packet in third segment 218 b and 218 c. Only configuration data packet in first segment 214 b and 214 c is described hereafter. Configuration data packet in first segment 214 b and 214 c includes a first field information 214 b and a second field information 214 c.

First receivers 120 can initially set up the first field information 214 b and second field information 214 c for “K27.7 SCT” and “K29.7 SCT.” According to one embodiment of the current disclosure, for example, first receivers 120 sets up first field information 214 b as zero value (0) and second field information 214 c as 0, 1, 2, 3, 4, and 5, which each value corresponds to one of second receivers 130, respectively, where six (6) second receivers 130 are serially arranged. First (1^(st)) second receiver 130 a receives zero value (0) of first field information 214 b and adds one (1) value thereto. First (1^(st)) second receiver 130 a then transmits the value of one (1) to next second (2^(nd)) second receiver 130 b and add one (1) value thereto again. Each second receivers 130 compares first field information 214 b and second field information 214 c whether they match or not. If first field information 214 b and second field information 214 c are matched, the second receiver 130 receives the data packet. If first field information 214 b and second field information 214 c does not match one another, the second receiver 130 does not receive that data packet. In this way, the second receiver 130 receives correctly assigned data and control command assigned to the second receiver 130. For instance, this protocol can be used for up to 256 (2 ⁸) second receivers serially connected to one another. However, the number is not limited to the above example. For example, if 12 bits are selected to express the field information, this protocol can be used for up to 4096 (2 ¹²) second receivers, which are serially connected to one another. Each of the second receivers' address and data is initially automatically programmed to be matched by the first receiver.

For example, referring now to FIG. 11 and FIG. 13A, at T1, the first (1^(st)) second receiver 130 a 1 is connected to the first receiver 120 a. The first (1^(st)) second receiver 130 a 1 recognizes that the first (1^(st)) field value of the 1^(st) “K27.7 SCT” is zero (0) and second (2^(nd)) field value is also zero (0). Since first (1^(st)) field value matches 2^(nd) field value, the first (1^(st)) second receiver 130 a 1 receives the data which are contained after the first (1^(st)) K27.7 SCT and replaces the first (1^(st)) field by adding one (1) and sends the modified content to next second (2^(nd)) second receiver 130 a 2. At T2, the second (2^(nd)) second receiver 130 a 2, which is connected to the first (1^(st)) second receiver 130 a 1, checks a first (1^(st)) field value of K27.7 SCT, which is one (1), and a second (2^(nd)) field value, which is also one (1). Since the first (1^(st)) field value matches second (2^(nd)) field value, the second (2^(nd)) second receiver 130 a 2 receives the data, which are contained after the second (2^(nd)) K27.7 SCT, and replaces the first (1^(st)) field by adding value one (1) and sends the modified content to next third (3^(rd)) second receiver 130 a 3.

At T3, the third (3^(rd)) second receiver is connected to the second (2^(nd)) second receiver 130 a 2 and checks the first (1^(st)) field value of the third (3^(rd)) K27.7 SCT. The first (1^(st)) field value is two (2) and the second (2^(nd)) field value is two (2). Since the first (1^(st)) field value matches the second (2^(nd)) field value, the third (3^(rd)) second receiver 130 a 3 receives the data, which is contained after the third (3^(rd)) K27.7 SCT, and replaces the first (1^(st)) field by adding value one (1) and sends the modified content to next second receiver 130 a 4. At T4 (not shown), the fourth (4^(th)) second receiver 130 a 4 is connected to the third (3^(rd)) second receiver and checks the first (1^(st)) field value of the fourth (4^(th)) K27.7 SCT. First (1^(st)) field value is three (3) and the second (2^(nd)) field value is three (3). Thus, the first (1^(st)) field value matches the second (2^(nd)) field value. Then, the fourth (4^(th)) second receiver receives the data, which is contained after the fourth (4^(th)) K27.7 SCT and replaces the first (1^(st)) field by adding value one (1) and sends the modified content to the next second receiver.

At T5 (not shown), the fifth (5^(th)) second receiver is connected to the fourth (4^(th)) second receiver and checks the first (1^(st)) field value of the fifth (5^(th)) K27.7 SCT. The first (1^(st)) field value is four (4) and the second (2^(nd)) field value is four (4). Since the first (1^(st)) field value matches the second (2^(nd)) field value, the fifth (5^(th)) second receiver receives the data, which is contained after the fifth (5^(th)) K27.7 SCT and replaces the first (1^(st)) field by adding value one (1) and sends the modified content to the next second receiver. At T6, the sixth (6^(th)) second receiver is connected to the fifth (5^(th)) second receiver and checks the first (1^(st)) field value of the (6^(th)) K27.7 SCT. The first (1^(st)) field value is five (5) and the second (2^(nd)) field value is five (5). Since the first (1^(st)) field value matches the second (2^(nd)) field value, the sixth (6^(th)) second receiver receives the data. Each and every second receiver 130 a compares the first (1^(st)) field value and second (2^(nd)) field value of the data packet 214 sent from the first (1^(st)) receiver 120 a. Each and every second receiver 130 a can be configured to receive the packet data if the first (1^(st)) field value matches the second (2^(nd)) field value but otherwise does not receive the data. Each of second receivers 130 a receives assigned data and control command assigned to the right second receiver 130 a. This protocol can cover up to 256 (2 ⁸) serially connected second receivers 130 a.

According to another embodiment of the current disclosure, as shown in FIG. 13B, the first field information 214 b have a number subtracted one (1) from a total number of the second receivers 130 a. It can be expressed as Y−1, where Y refers to the total number of second receivers 130. Second field information 214 c is set up to indicate an address of a targeted second receiver to which configuration data packet 210 is designated to convey. For example, if configuration data packet 210 is designated to X^(th) second unit receiver, a value of second field information 214 c can be set as Y-X.

In particular, for example, one of first receivers 120 a can set up first field information 214 b to have a value of five (5) value—a total number (6) of second receivers 130 a minus one (1). Regarding second field information, the total number of second unit receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, 130 a 5, and 130 a 6 in first module 130 a is six (6), and thus Y is six (6). If configuration data packet 210 is designated to sixth (6^(th)) second unit receiver in first module 130 a 6, second field information 214 c can be set as zero (0), Y(6)-X(6). In another example, if configuration data packet 210 is designated to second (2^(nd)) second receiver 130 b 2 in second module 130 b, second field information 214 c can be set up as four (4), Y(6)-X(2). In the other example, if configuration data packet 210 is designated to fourth (5^(th)) second receiver 130 c 5 in third module 130 c, second field information 214 c can be set as one (1), Y(6)-X(5).

Set of field information of the configuration data packet 214 b and 214 c are configured to be changed sequentially by adding or subtracting a predetermined value therefrom when passed in or out of at least one second receiver 130 a 1. Referring to FIGS. 4 and 13 A/B, the present disclosure describes a method in which data are transmitted from first receivers 120 a to sixth (6^(th)) second receiver 130 a 6 in first module 130 a; from first receivers 120 a to second (2^(nd)) second receiver 130 b 2 in second module 130 b; and/or from first receivers 120 a to fifth (5^(th)) second receiver 130 c 5 in third module 130 c, respectively.

First (1^(st)) second receiver 130 a 1 coupled to first receiver 120 a receives configuration data packet 210. Configuration data packet 210 is designated to sixth (6^(th)) second receiver 130 a 6 in first module 130 a. As explained above, first field information of second receivers 130 a is five (5). Ordered pair of first and second field information is (5, 0) as indicated in FIG. 13B. First (1^(st)) second receiver 130 a 1 compares first field information 214 b (5) and second field information 214 c (0). If first field information 214 b and second field information 214 c have the same value, then first (1^(st)) second receiver 130 a 1 receives and processes configuration data packet 210. Since first field information 214 b (5) and second field information 214 c (0) do not match one another, first (1^(st)) second receiver 130 a determines that configuration data packet 210 is not designated thereto. Consequently, first (1^(st)) second receiver 130 a does not process or execute configuration data packet 210 and passes the same onto next receiver, which is second (2^(nd)) second receiver 130 a 2. When configuration data packet 210 passes in or out, first (1^(st)) second receiver 130 a 1 subtracts a predetermined value from first field information 214 b. For example, if the predetermined value is one (1), first field information 214 b is changed from five (5) to four (4). Thus, ordered pair of first field information 214 b and second field information 214 c now becomes (4, 0). After the subtraction, first (1^(st)) second receiver 130 a 1 passes configuration data packet 210 onto next second (2^(nd)) second receiver 130 a 2. Second (2^(nd)) second receiver 130 a 2 compares first field information 214 b (5) and second field information 214 c (0). As such, first field information is four (4) and second field information is zero (0). It does not match one another. Thus, second (2^(nd)) second receiver 130 a 2 makes ordered pair of first and second field information from (4, 0) to (3, 0), and passes configuration data packet 210 onto next receiver.

As illustrated in FIG. 13B, when configuration data packet 210 arrives at sixth (6^(th)) second receiver 130 a 6, ordered pair of first field information 214 b and second field information 214 c becomes (0, 0). Sixth (6^(th)) second receiver 130 a 6 compares first field information 214 b (0) and second field information 214 c (0). They both now have the same value of zero (0). Thus, sixth (6^(th)) second receiver 130 a 6 determines that configuration data packet 210 is designated to sixth (6^(th)) second receiver 130 a 6, and processes or executes any predetermined actions. Such process or execution can include read and write configuration data packet 210 from or onto a memory (not shown) that resides in sixth (6^(th)) second receiver 130 a 6. In doing so, first receiver 120 a can transmit configuration and image data packet 210 and 220 to the designated sixth (6^(th)) second receiver 130 a 6. This protocol can be used for up to 256 (2⁸) serially connected second receivers. However, the number is not limited to the above example. For example, if 12 bits are selected to express the field information, this protocol can be used for up to 4096 (2¹²) serially connected second receivers. Each of the second receivers' address and data is initially automatically programmed to be matched by the first receiver.

Configuration data packet 210 and/or image data packet 220 include(s) numerous commands, which are defined for LED driver 140 and for flash memory control. Commands can be defined by a host personal computer or send box. Commands can be broadcasted to first receivers 120 and be transmitted to second receivers 130. Second receivers 130 can generate pattern system clocks and data receiving control signal for LED drivers 140 based on the reference clock from first receivers 120. The pattern system clocks and data receiving control signals for LED driver 140 are generated by each of second receivers' 130 Clock and Data Recovery (CDR) block. Each of second receivers 130 does need a reference clock from the first receivers 120 to keep the frequency accurate.

FIG. 13B shows another example of how configuration data packet 210 is transmitted from first receivers 120 a to second (2^(nd)) second receiver 130 b 2 in second module 130 b. In FIG. 10, the ordered pair of first and second field information is (5, 4). According to the process described above with respect to Sixth (6^(th)) second receiver 130 a 6, second (2^(nd)) second receiver 130 b 2 in second module 130 b compares first field information 214 b (4) and second field information 214 c (4). Since first field information 214 b (4) and second field information 214 c (4) have same value, second (2^(nd)) second receiver 130 b 2 determines that configuration data packet 210 is designated thereto, and performs necessary process with configuration data packet 210. And then, second (2^(nd)) second receiver 130 b 2 subtracts one from first field information passes configuration data packet onto next third (3^(rd)) second receiver 130 b 3. Regarding other second receivers 130 b 1, 130 b 3, 130 b 4, 130 b 5, and 130 b 6 in second module 130 b, each of them determines that first field information 214 b does not match with second field information 214 c. Thus, each of other second receivers 130 b 1, 130 b 3, 130 b 4, 130 b 5, and 130 b 6 in second module 130 b passes configuration data packet 214 b onto next second receiver.

FIG. 13B illustrates still another example of how configuration data packet 210 is transmitted from first receivers 120 a to fifth (5^(th)) second receiver 130 c 5 in third second receiver module 130 c. Ordered pair of first and second field information is (5, 1). All second receivers 130 c 1, 130 c 2, 130 c 3, 130 c 4, 130 c 5 and 130 c 6 in third second receiver module 130 c subtract one from first field information and passes configuration data packet 210 onto next second receiver. Only the fifth (5^(th)) second receiver 130 c 5 processes and executes configuration data packet 210.

FIG. 14 is a block diagram showing a calculation of V_(sync) signal delay value. It is important to distribute data and signals across plurality of LED drivers in a synchronized manner. V_(sync) signal can be used as an alignment flag among LED drivers. A latency among the LED drivers could cause a command synchronization problem. In this regard, a configuration register of “V_(sync) delay” can be defined as a synchronization number and by adjusting the value of synchronization number, synchronization problem can be overcome.

First module 130 a can include six (6) serially arranged second receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, 130 a 5, and 130 a 6. Latency from each of second receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, 130 a 5, and 130 a 6 to LED drivers can create synchronization problems. To attenuate such latency problems, set of field information 214 b and 214 c can be used. Configuration data packet 210 can include a delay value which reflects the change of first field information 214 b. Thus, each of second receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, 130 a 5, and 130 a 6 can determine a period of delay time transmitting at least one of configuration data packet 210 and/or image data packet 220 to LED drivers 140 according to a set delay value.

In particular, referring to FIG. 14, first (1^(st)) second receiver 130 a 1 coupled to first receiver 120 a receives configuration data packet 210. First field information 214 b of configuration data packet 210 is five (5) as explained above. Second field information has a synchronization number. The synchronization number can be any pre-defined number and is distinguishable from general second field number 214 c. For example, the synchronization number can be two hundred fifty-five (255). Thus, when any second receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, 130 a 5, and 130 a 6 receive set of field information having the synchronization number, they recognize first field information 214 b as delay value.

Referring to FIG. 14, first (1^(st)) second receiver 130 a 1 receives the synchronization number (255). First (1^(st)) second receiver 130 a 1 reads value of first field information 214 b as delay value. When configuration data packet 210 passes onto next second receiver, first (1^(st)) second receiver 130 a 1 subtracts a predetermined value from first field information 214 b. Where the predetermined value is one (1), the value of first field information 214 b changes from five (5) to four (4).

Second (2^(nd)) second receiver 130 a 2 receives first field information 214 b, which is now four (4), and recognizes it as a delay value. Likewise, delay value for second receivers 130 a 3, 130 a 4, 130 a 5, 130 a 6 are three (3), two (2), one (1), and zero (0), respectively.

Since sixth (6^(th)) second receiver 130 a 6 has zero (0) delay value, when the sixth (6^(th)) second receiver 130 a 6 transmits data and signals to LED drivers 140, the transmission time becomes a synchronization time for other second receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, and 130 a 5. Accordingly, when first (1^(st)) second receiver 130 a 1 transmits data or signal to LED drivers 140, it uses the delay value (5) to calculate a period of a delay time so that the transmission time of data from first (1^(st)) second receiver can be synchronized with the synchronization time according to the delay time. In a similar way, transmission times from each of second receivers 130 a 1, 130 a 2, 130 a 3, 130 a 4, and 130 a 5 can be synchronized with the synchronization time of sixth (6^(th)) receiver 130 a 6.

FIG. 15 is a graph showing a configuration data modulation and a synchronization thereof. Referring to FIG. 15, six different signals are depicted with latencies in Period A. Each of signals comes with a respective delay value, which is calculated in a manner as described in FIG. 14. Each of signals is delayed for a period of the delay time based on the relative delay value. Period B in FIG. 15 depicts synchronized six signals at the synchronization time after the period of the delay time.

FIG. 16 is a schematic flowchart of the method for transmitting data packet using an LED display device that includes transmitter 110, at least one first receiver 120, a plurality of second receiver modules.

Step 310 refers to a step of sending at least one of a configuration data packet and an image data packet from the transmitter 110 to one of the plurality of second receiver modules. Each of the configuration and image data packets includes a set of field information. Step 320 refers to a step of receiving the at least one of the configuration and image data packets. Step 330 refers to a step of sending one of the configuration and image data packets to one of the plurality of modules. Step 340 refers to a step of determining whether the at least one of the configuration and image data packets are designated thereto. Step 350 refers to a step of processing one of the configuration and image data packets. Step 360 refers to a step of changing the set of field information by sequentially adding or subtracting a predetermined value therefrom when entering or exiting the at least one second receiver. The configuration data packet includes configuration data while the image data packet includes image data.

It is to be understood that the exemplary embodiments described herein are that for presently preferred embodiments and are not limiting. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. 

1-20. (canceled)
 21. An LED display device comprising: an LED display having an array of LED pixels; a transmitter having a memory and a pixel mapping table, wherein the pixel mapping table receives a data packet from a data source and assigns to the data packet a set of field information that contains a unique address for a LED pixel in the array of the LED pixels; a plurality of first receivers coupled to the transmitter; a plurality of second receiver modules, each comprising a plurality of second receivers, wherein each of the second receiver modules is coupled to at least one of the first receivers and receives the data packet therefrom; and a plurality of LED driver groups, each comprising a plurality of LED drivers that drive the array of LED pixels, wherein each of the LED driver groups is coupled to one of the plurality of second receivers and transmits the data packet received from the second receiver to the LED pixel, wherein none of the plurality of second receivers comprises an external volatile memory.
 22. The LED display device of claim 21, wherein one or more of the plurality of second receivers comprises a flash memory.
 23. The LED display device of claim 21, wherein none of the plurality of second receivers comprises a pixel mapping memory.
 24. The LED display device of claim 21, wherein each of the second receivers reads the set of field information in the data packet and determines whether the data packet is designated to the second receiver that reads the data packet.
 25. The LED display device of claim 21, wherein the set of field information is configured to change sequentially by adding or subtracting a predetermined value therefrom when the set of field information enters or exits each of the second receivers.
 26. The LED display device of claim 21, wherein the second receivers are serially arranged in one of the plurality of second receiver modules, wherein the set of field information further comprises a first field information and a second field information, wherein the first field information has a first number subtracted one from a total number of the serially arranged second receivers, and wherein the second field information has a second number of a sequential order number of a designated second receiver.
 27. The LED display device of claim 21, wherein each one of the second receivers compares the first field information with the second field information and determines whether the set of field information is designated thereto based on whether the first field information and the second field information match.
 28. The LED display device of claim 21, wherein the second receivers are serially arranged in one of the plurality of second receiver modules, wherein the set of field information further comprises a first field information and a second field information, wherein the first field information includes a first value and the second field information includes a second value, wherein each of the second receivers is compares the first value to the second field value, and when the first number is not the same as the second number, the first number is increased by an increment of a value one (1) and the set of field information is transmitted to an adjacent second receiver, and wherein the second field information has a second number of a sequential order number of a designated second receiver.
 29. The LED display device of claim 21, wherein the at least one of the first receivers communicates with at least one of the second receivers via a Low Voltage Differential Signaling (LVDS) connection.
 30. The LED display device of claim 21, wherein at least one of the first receivers sends a source clock to at least one of the second receivers via a low-bandwidth phase-locked loop (PLL).
 31. The LED display device of claim 21, wherein the data packet comprises a first segment comprising the first field information, a second segment comprising a data information, and a third segment comprising the second field information, wherein the first, second, and third segments are sequentially arranged.
 32. The LED display device of claim 31, wherein the first segment further comprises a start of frame and a data mode information.
 33. The LED display device of claim 32, wherein the third segment further comprises an end of frame and the data mode information.
 34. The LED display device of claim 21, further comprising a transformerless wire link connecting one of the plurality of first receivers to one of the plurality of second receiver modules to transmit data therebetween.
 35. The LED display device of claim 21, wherein the transformerless wire link is a serializer/deserializer (SerDes) link.
 36. The LED display device of claim 21, wherein each of the plurality of second receivers includes a phase-locked loop (PLL).
 37. The LED display device of claim 21, wherein a distance between the plurality of first receivers and the plurality of second receiver modules is less than 4 m.
 38. The LED display device of claim 21, wherein a distance between the adjacent receivers of the plurality of second receivers is less than 4 m.
 39. The LED display device of claim 21, wherein the transmitter is connected to the plurality of first receivers via a Gigabit Ethernet PHY (GPHY).
 40. The LED display device of claim 21, wherein adjacent second receivers in one or more of the plurality of second receiver modules are connected via a serializer/deserializer (SerDes) link. 